Current known die stacking arrangements rely on formation of a metallurgical joint between die interconnect bumps and pads on abutting front surfaces of joined die. Preparation of the metallurgical joint can require complex plating finishes to be applied to the bump and/or die surface under high temperature and pressure. The die include upper and lower planar surfaces, and stacking is such that an upper planar die surface will support the lower planar surface of a subsequently stacked die.
There has been some development in the art of thru silicon vias (TSV), in which a via is etched in a die and the etched via is filled with a conductor. The conductor filled TSVs provide an electrical path by which electrical current can pass directly through the die, between two opposing sides thereof. Because TSVs allow for the shortest electrical path between two sides of the die, they have been used for three-dimensional stacking as well as for RF and MEMS wafer level packaging (WLP).
In the art of TSVs there are two basic processes that can be used for forming interconnects. These processes include via-last processing and via-first processing. In the via-last processing, interconnects are formed after a back end of line (BEOL) processing is completed. In the via-first processing, vias are formed prior to thinning the wafer and incorporating semiconductor components into the device. In the via-last approach, the substrate is thinned and some semiconductor components can be incorporated into the device prior to forming vias. Each process has its own unique characteristics. For example, in via-first processing, vias can be formed with a front side etch; while via-last processing can form vias with a back side etch. Front side etching renders characteristic markings on the substrate, whereas back side etching renders characteristic markings distinguishable from that of front side etching.
There continues to be a need for improved packaging in applications such as cellular phones, personal digital assistants (PDAs), and other small-form-factor products. At least four methods are currently used to devise a chip stack including die-to-die, package-to-package, die-to-wafer and wafer-to-wafer. These stacking methods, even with the inclusion of TSVs, continue to rely on formation of a metallurgical joint between die interconnect bumps and pads formed on the planar outer surface of the die. Accordingly, time consuming and costly steps are required to complete the metallurgical bonding between adjacent planar die surfaces.
As such, there is a need for a simple process that enables easier die stacking during semiconductor package assembly without relying solely on bumps and pads to interconnect planar surfaces of adjacent die.